This invention is directed to a semiconductor integrated power-on reset circuit and in particular to a semiconductor integrated power-on reset circuit that is formed on the same monolithic substrate as the digital circuitry same is adapted to reset to a predetermined binary state in order to realize higher component density and the elimination of discrete circuit components required for use with the monolithic substrate.
Heretofore, digital electronic instrumentation, such as electronic timepieces, calculators and the like that are formed on a single monolithic substrate having complementary coupled P-channel and N-channel MOS field effect transistors, hereinafter referred to as "C-MOS transistors" have not been provided with a reset circuit that automatically references the digital circuitry to a predetermined binary state at the time that the power applied to the digital circuitry is turned on. One reason is that power-on reset circuits of the type known in the prior art would reduce the component density on the monolithic substrate or alternatively would require additional discrete circuit elements to be coupled to the substrate.
Moreover, the absence of such power-on reset circuits lessens the reliability of such digital circuitry. For example, in electronic digital timepieces, if a power-on reset circuit is not provided, a considerable period of time is required to determine if the timepiece had been accurately set to a predetermined binary state when the power is turned on. Similarly, in an electronic calculator, the absence of a power-on reset circuit prevents the respective registers and counters thereof from being set to a predetermined zero state when the power source of the calculator is turned on. Accordingly, a power-on reset circuit that is formed on the same circuit chip as the circuitry that same is adapted to reset, that realizes higher component density on the circuit chip and that eliminates the additional discrete circuit components required for use with the circuit chip is desired.